SRAMs are read/write memories capable of holding data without the need for frequent refreshing of the contents of the memory cells in the SRAM. In a conventional SRAM, the memory cells are arranged in a series of rows and columns. Referring to FIG. 1, which shows the basic structure of the memory array of a conventional SRAM 10, in each column 12, all the memory cells 14 are coupled between a BIT line 16 and a BIT line 18. FIG. 1 shows only one column, that column comprising two column segments 12a and 12b that are alternately selectable via a column select signal 20 that is decoded from the address. However, it should be understood that a typical SRAM comprises many columns. Further, the purpose of segmenting the columns in the manner shown is related to implementation details and particularly to reducing the physical length of the columns relative to the physical width of the memory array. Thus, it should further be apparent to those of skill in the related arts that many SRAMs have simple rows and columns without segmentation.
Each column segment comprises N rows 22 of which only the first row (row 0) and the last row (row N-1) are shown. Each row is coupled to a word select line 24 (sometimes called a row select line) RL(0) through RL(N-1). The signals on the row select lines 24 are decoded from the address to select a particular row in the memory array. A particular column containing the memory cell being accessed also is decoded from the address to select the single memory cell for reading via a plurality of column select lines, such as column select line 20.
The BIT lines 16 of each column segment of a single column are coupled together and placed at one input of a sense amplifier 26. The BIT lines 18 of each column segment of a column are coupled together and placed at the second input of the sense amplifier 26. Each column in a multi-column memory has its own sense amplifier. The sense amplifier 26 is controlled by a READ control line. Specifically, the sense amplifier output is latched when the READ line goes unasserted.
In a segmented column memory array as illustrated in FIG. 1, transistor switch 28a is interposed between each BIT line 16 and the first input of the sense amplifier and another transistor switch 28b is interposed between each BIT line 18 and the corresponding input of the sense amplifier for selecting the one of the two column segments containing the cell which is being accessed by the address. The switches 28a and 28b are coupled to react complementarily to the same column select signal lines, i.e., CSEL-A 20 and its compliment CSEL-A. The column select signal essentially is another portion of the decoded address.
Each column segment further comprises a precharge circuit 34 for precharging both the BIT and BIT lines 16 and 18 of the column segments 12a and 12b to the same predetermined voltage before a read operation. Particularly, the individual memory cells 14 are coupled between the BIT and BIT lines of the corresponding column segment such that, during a READ, the cell selected by the decoded address, i.e., the row select line signals 22 and column segment select signals 30 will discharge one and only one of the BIT and BIT lines depending on whether it is storing a 0 or a 1. The BIT line represents the true value of the stored BIT, while the BIT line is its complement. All control signals, including the decoded address signals, such as row select and column select, the precharge signal, and the READ signal are shown emanating from a control circuit 37.
When a cell 14 is read, the sense amplifier 26 detects the differential between the relevant BIT and BIT line pairs 16 and 18, latches those values (at the time that the READ line goes unasserted) and amplifies and outputs the corresponding bit value.
The purpose of precharging the BIT and BIT lines is to reduce the time necessary to read a cell. In particular, it takes substantially more time for a cell to charge a line than it does to discharge it. Accordingly, prior to a READ, both lines are charged by the precharge circuit and the READ operation comprises discharging one of the BIT and BIT lines.
With the ever present desire to increase memory capacity and speed, many SRAMs currently utilize additional techniques to further decrease READ times. In particular, one class of techniques revolves around the concept of completing the READ before the BIT or BIT line is completely discharged. In particular, the sense amplifiers typically used in SRAMs require a relatively small voltage differential between their inputs to switch (or, more accurately, to detect the differential between the BIT and BIT lines coupled at their inputs). For instance, a typical detectable differential voltage threshold across the inputs of a sense amplifier might be about 400 millivolts.
Within this class, there are at least three techniques that are in common use for cutting short the discharge time involved with the READ operation. They are (1) bit line clamping, (2) controlling the on time of the cell access transistors with a delay circuit and (3) controlling the on time of the cell access transistors using a dummy column as a reference. Each of these techniques will be briefly described below. However, those of skill in the art of SRAM design will already be familiar with each of these techniques.
Bit clamping is a technique by which the BIT and BIT lines are precharged to some voltage less than the VDD (or VSS) voltage. The theory behind bit line clamping is to precharge the BIT and BIT lines to a voltage only slightly above the necessary threshold voltage for detecting a differential across the sense amplifier. For instance, in a 3 volt circuit (VDD=3 volts and VSS=0 volts,) let us assume that the switch point between a logic high value and a logic low value is 1.5V. Accordingly, with BIT clamping, the BIT and BIT lines may be precharged to only about 1.8 volts rather than 3 volts. Accordingly, the discharged line (BIT or BIT) can reach the threshold value much more quickly than if it had been precharged to 3 volts.
FIG. 2 is a circuit diagram of an exemplary precharge circuit employing bit line clamping. As previously noted, the precharge circuit 202 is coupled between the BIT line 204 and the BIT line 206 of the corresponding column (or column segment). The precharge circuit is of a form conventional in the art and comprises three NMOS transistors 208, 210 and 212. Normally, the junction 214 between the transistors 210 and 212 would be coupled directly to the VDD voltage rail. However, with bit line clamping, a diode-coupled PMOS transistor 216 is coupled between VDD and junction 214. This lowers the voltage to which the precharge circuit will precharge the BIT and BIT lines 204 and 206 by the threshold voltage of the PMOS transistor 216. A typical threshold voltage for a PMOS transistor might be 0.6V. Accordingly, in this circuit implementation, the precharge voltage is 2.4 volts rather than 3 volts. If it was desired to drop the precharge voltage from a VDD of 3 volts to, for example, 1.8 volts as discussed previously, there would simply be two BIT line clamping diode coupled transistors coupled in series between VDD and node 214.
FIG. 3 illustrates an exemplary embodiment of the second aforementioned technique, i.e., controlling the on time of the cell access transistors with a delay. The theory behind this technique is to stop the READ operation and latch the sense amplifier after a sufficient time elapses to assure that the voltage differential across the sense amplifier inputs exceeds the minimum necessary threshold, but before the BIT or BIT line discharges completely. To implement this concept, the READ control line 302 (and possibly other of the control lines such as the row select line 306 and column select line 308) are not only fed directly from the control circuit 305 to their normal destinations within the memory array 303, but also fed through a delay circuit 304. The delay circuit typically may comprise a chain of inverters (or inverter equivalents). When the values of these signals change, the outputs of the delay circuit will not match the true value of those signals for the delay period of the delay circuit 304. After the delay period established by the delay circuit, the undelayed signals and the corresponding delayed signals will match again. When they match again, the READ is considered completed and the sense amplifiers are latched. The delay period is predetermined during the design of the circuit and is selected to be at least as long as the longest possible period needed to read a cell in the SRAM. Even the longest possible READ time for the memory is usually significantly shorter than the time required to completely discharge the BIT or BIT line.
FIG. 4 illustrates the third above mentioned technique for minimizing read discharge and precharge times. In this technique, a dummy column 402-N is added to the end of the memory array (the term end signifies the longest distance in terms of signal propagation delay from the source of the control lines (e.g., read, row select and column select) to the column. All of the memory cells in the dummy column 402 are written with the same data (0 or 1). Preferably, if the idle mode of the sense amplifier 406 is logic 1 during the write or precharge cycle, the dummy cells are written with logic 0 and vice versa. The dummy column 402 has its own sense amplifier 406-N. Thus, whenever a READ operation is executed, the output of the sense amplifier 406-N always makes a high to low transition. The output of the sense amplifier 406-N of the dummy column is forwarded to the control circuit 408 where it is detected. Upon detection, the READ operation is ceased, i.e., the sense amplifier is latched by deasserting the READ control line 410. As noted above, the dummy column is placed at the end of the memory array so that the read access delay set by the dummy column is greater than the read access delay of any other column. This guarantees that, when the READ operation is halted, the sense amplifier corresponding to the actual cell being read has switched.
All the aforementioned techniques for minimizing read time have certain disadvantages. For instance, the bit line clamping technique becomes less feasible in connection with low voltage (less than 1.5V) designs because this technique reduces the bit line operational voltage by the threshold voltage of the bit line clamping transistor or transistors. Depending on the particular design of the sense amplifier used in the SRAM, there are different problems. For instance, if there is a clamping diode connected to the sense amplifier in series with the power supply VDD/VSS, the output voltage of the sense amplifier will be VDD-V.sub.T (where V.sub.T represents the threshold voltage of the BIT line clamping transistor). This voltage level could cause DC power to dissipate during a read operation, and drive the next gate with an intermediate voltage.
In a case where there is no clamping diode connected to the sense amplifier in series with the power supply, there is no danger of the sense amplifier driving the next gate with an intermediate voltage as in the previous case. However, the precharge voltage level of the BIT and BIT lines are V.sub.T below the precharge level of the inputs to the sense amplifiers (assuming a single PMOS diode transistor used as the BIT line clamp). Thus, as the BIT line access transistors turn BIT on, an instantaneous charge sharing would occur between input nodes of the sense amplifier and the BIT and BIT lines. Accordingly, the inputs to the sense amplifier start to move towards VDD-V.sub.T. Therefore, if there are mismatches in (parasitic) capacitance lines among the BIT lines and among the sense amplifier inputs, the sense amplifier might swing in the wrong direction. Once the inputs to the sense amplifier swing toward the wrong direction, the sense amplifier (which usually comprises a cross coupled circuit design) will make a wrong decision and will push the BIT line further in the wrong direction. If the transconductance of the load transistors in the sense amplifier is higher than that of the load transistors in the memory cells, the memory cell data could be overwritten with wrong data. Thus, while performing a read operation, it could overwrite the cell data and produce a wrong value at the output of the sense amplifier.
In connection with the second technique, i.e., controlling the on time of the read operation with a delay circuit, the delay circuit needs to be individually designed for each operating condition and for each specific memory size. Accordingly, the circuit is not transferable from one design to the another and must be redesigned for each different SRAM to which the technique is applied. Furthermore, if the operation environment conditions change due to a voltage or temperature drift such that the read access time becomes longer than the delay time, the SRAM will cease to function at all.
Finally, the third technique, i.e., using a dummy column, also has shortcomings. First, it requires extra die area to implement. Secondly, it dissipates extra power to precharge and discharge the BIT and BIT lines in the dummy column. Thirdly, it adds extra delay on the row select lines to drive the cells of the dummy column (which comprise an extra column at the end of the real columns).